Patent · US Expired

Process for manufacturing a package for mating with a bare semiconductor die

US5589402A · kind A · utility

7Cited by

23References

20Claims

0Family size

Assignee

Motorola, Inc. · US

Inventors

Kenneth C. Ramsey · Gilbert, US
William J. Miller · North Wales, US
William Strom · Chandler, US

Key dates

Filing date	Oct 30, 1995
Grant date	Dec 31, 1996
Priority date	—
Expiry date	Oct 30, 2015

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T29/49121
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for interconnecting electrical system components. A leadframe (10) having leads (11) is encapsulated within a molding compound to form a first section (36) of the interconnect package (35). The first section (36) optionally includes channels (54). A leadframe (20) having leads (22, 23) is encapsulated within a molding compound to form a second section (37) of the interconnect package (35). The first and second sections (36 and 37, respectively) are coupled together with an adhesive material (43). An end (44) is removed from the interconnect package (35) forming an edge (50). A bare semiconductor chip (51) is coupled to the edge (50).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.