Field-testable integrated circuit and method of testing
US5589766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Apr 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A field-testable integrated circuit that includes a plurality of analog signal channels for receiving a respective analog signal during a normal mode of operation is provided. Individual test circuits are built-in within the integrated circuit for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels. Each test circuit includes a channel decoder responsive to predetermined channel select signals for producing a respective channel decoder output signal. A multiplexer is responsive to predetermined reference select signals and to the decoder output signal for supplying during the test mode of operation a selected one of the predetermined reference signals to the respective analog channel being coupled to the individual test circuit therein. A switching gate is responsive to the respective channel decoder output signal so that during the normal mode of operation the switching gate is in a respective conducting state for allowing the respective analog signal to pass therethrough while during the test mode of operat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.