Bus driver circuit for high-speed data transmission
US5589789A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1994 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Oct 17, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.