Method and arrangement for transformation of signals from a frequency to a time domain
US5590067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Mar 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot. 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot. 2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common pro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.