Method of and apparatus for improved dynamic random access memory (DRAM) providing increased data bandwidth and addressing range for current DRAM devices and/or equivalent bandwidth and addressing range for smaller DRAM devices
US5590078A · kind A · utility
Inventor
Key dates
| Filing date | Oct 7, 1994 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Oct 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and apparatus for improving the accessing capability of asynchronous and synchronous dynamic random access memory devices by a novel interfacing and accessing procedure in which the same pins are used for each of row, column and data accessing and in both the write and read cycles; such enabling effective increasing of the data bandwidth and addressing range in substantially the same size packages and pin counts of current DRAMs, or providing equivalent performance in smaller packages with fewer pins. This enables reducing the number of required components for the same configuration, providing compatable density in smaller packages, and with lower power consumption and finer granularity and pin compatability for a wide range of current DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.