Method for detecting addressing errors in an electrical unit
US5590278A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1994 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | May 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting addressing errors in an electrical unit. The electrical unit may, e.g., include a central processing unit and modules that respond to the central processing unit via a communication system by means of addresses specific to the modules. Addressing errors caused by faulty modules can be detected. For at least a portion of the accesses made by the central processing unit on one of the modules, an identifier is transmitted from the addressed module to the central processing unit. The identifier transmitted to the central processing unit is compared to a reference identifier. Addressing errors are recognized when the transmitted identifier deviates from the reference identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.