Clock doubler and smooth transfer circuit
US5590316A · kind A · utility
Inventor
Key dates
| Filing date | May 19, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | May 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed for smoothly multiplying the frequency of a computer's basic clock during a burst transfer cycle and smoothly resuming the basic clock frequency upon completing the burst transfer cycle. A fixed frequency multiplier is connected to the basic clock to generate a clock whose frequency is a multiple of the basic clock frequency. A decoder which operates synchronously with the fixed frequency multiplier clock responds to control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder also toggles a speed-up signal during the burst transfer cycle on the rising edges of the fixed frequency multiplier clock. The speed-up signal and the basic clock is provided to a variable frequency multiplier which multiplies the frequency of the basic clock when the speed-up signal is toggled and reproduces the frequency of the basic clock when the speed-up signal is deasserted, thus providing a clock signal whose rising edges are aligned with the rising and falling edges of the basic clock and whose frequency is a multiple of the basic clock frequency during the burst transfer cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.