Protocol parallel processing apparatus having a plurality of CPUs allocated to process hierarchical protocols
US5590328A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Mar 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A protocol processing apparatus is presented having a plurality of CPUs for processing communication protocol data in parallel so as to achieve a high measure of efficiency. The apparatus provides a common memory including a CPU state table that is accessible by the plurality of CPUs. The CPU state table associates an idle flag, a remote node identifier, and a process start time with each of the plurality of CPUs. At least one line interface selects a CPU from the plurality of CPUs according to the contents of the CPU state table, selecting an idle CPU if one is available, selecting a CPU with the oldest process start time if no idle CPU is available, or selecting a busy CPU if the communication data to be processed is related to communication data already running on the busy CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.