Bus supporting a plurality of data transfer sizes and protocols
US5590369A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Aug 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus for transferring data is disclosed wherein the bus supports asynchronous, synchronous and high speed synchronous data transfers of varying size. The bus includes a master component for controlling data transfers with one or more slave components attached to the bus. Each data transfer is either received or supplied by the master via a set of data lines common to each slave component. Further, there are different control lines between the master and the slave components depending on the protocol(s) supported by each of the slaves. In particular, a slave supporting a high speed synchronous protocol is connected to the master by four control lines dedicated to providing control signals for implementing a high speed synchronous protocol handshake. Further, a fifth such control line is used to select a slave for a high speed synchronous data transfer when there is a plurality of high speed synchronous slaves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.