Intelligent memory system for processing varibable length I/O instructions
US5590370A · kind A · utility
30Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Nov 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system contains one or more active storage elements. Each active storage element includes a memory element and a processing element associated with the memory element. The memory element contains microcode for implementing a specific function. A first bus connects the processing element to a host processor. A second bus connects the processing element to a peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.