Multiprocessor system with processor arbitration and priority level setting by the selected processor
US5590380A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to this invention, an interrupt right control unit transfers an interrupt right to a succeeding processor module. When the processor module has the interrupt right, and the interrupt right control unit receives an interrupt signal, the interrupt right control unit outputs an interrupt signal to a corresponding processor and stops transferring the interrupt right. The corresponding processor then sets the priority levels for the processor modules and performs interrupt processing in response to the interrupt signal. Then the corresponding processor causes the interrupt right control unit to continue the transferring of the interrupt right.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.