Phase comparison circuit for maintaining a stable phase locked loop circuit in the absence of the pulse of an input signal
US5592110A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1995 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Apr 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase comparison circuit used in a phase locked loop circuit which realizes a stable phase locked loop circuit without changing the output frequency of a voltage-controlled oscillator, even if an input pulse is missing. The phase comparison circuit includes a circuit for generating a first pulse at each rising edge of an input signal, a circuit for generating a second pulse at each falling edge of the input signal, a circuit for generating a third pulse at each falling edge of a reference signal, a circuit for generating a first output signal from the first pulse and the second pulse, and a circuit for generating a second output signal from the first pulse and the third pulse. The output signals are not increased even if an input pulse is missing so that the operation of the phase locked loop circuit remains stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.