Clock speed limiter for an integrated circuit
US5592111A · kind A · utility
15Cited by
20References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1994 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.