GPS receiver having a low power standby mode
US5592173A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1994 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Jul 18, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A GPS receiver having a normal mode to receive GPS satellite signals and to provide location information, and a low power standby mode. A microprocessor system in the GPS receiver causes the GPS receiver to alternate between the normal mode and the low power standby mode in order to reduce the average power consumption in the GPS receiver. In the normal mode a GPS antenna receives GPS satellite signals, the GPS frequency downconverter converts the frequency of the GPS satellite signals to an intermediate frequency, a digital signal processing system processes the intermediate frequency to provide GPS satellite signal correlation information. The microprocessor system processes the correlation information and provides location information to a user. In the standby mode, the operating power is inhibited in the GPS antenna and the GPS frequency downconverter, the system clock is inhibited in the digital processing system, and the microprocessor clock is inhibited in the microprocessor system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.