High resolution image processor with multiple bus architecture
US5592237A · kind A · utility
154Cited by
6References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 4, 1994 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Nov 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K.times.2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.