Nonvolatile memory
US5592409A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 1995 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Jan 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Nonvolatile memory with a simple structure where recorded information can be read without destruction: Voltage is impressed between control gate CG and memory gate MG at a writing operation. A ferroelectric layer 32 is polarized in accordance with the direction of the impressed voltage. The control gate voltage V.sub.CG to make a channel is low when the ferroelectric layer 32 is polarized with the control gate side being positive (polarized with second status). The control gate voltage V.sub.CG to make a channel is high when the ferroelectric layer 32 is polarized with the control gate side being negative (polarized with the first status). The reference voltage V.sub.ref is impressed to the control gate CG at the reading operation. A high drain current flows when the ferroelectric layer is polarized with the second status and low drain current flows when the ferroelectric layer is polarized with the first status. Recorded information can be read by detecting the drain current. With this reading operation, the polarization status is not destroyed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.