Memory cell circuit independently controlled in writing and reading
US5592414A · kind A · utility
9Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1995 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Oct 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell circuit which enables reduction of the leak current between a bit line and a memory cell and enables realization of a high speed reading operation and writing operation, wherein a write only circuit and a read only circuit are constructed by a drive transistor and a select transistor, the drive transistor comprising an enhancement type transistor with a threshold voltage set lower than the threshold voltage of the select transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.