Technique for accelerating instruction decoding of instruction sets with variable length opcodes in a pipeline microprocessor
US5592635A · kind A · utility
14Cited by
13References
31Claims
0Family size
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Key dates
| Filing date | Jul 15, 1994 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Jul 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions concurrently while they are being fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.