Logic simulation method
US5592655A · kind A · utility
3Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1994 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Nov 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For simulation evaluation of combinational logic, changes in input signals are reserved for events occurring with respect to every element of the combinational logic circuit or of a partial circuit within the logic circuit according to demand timing. To inhibit wasteful processes, when the output value of a pertinent element or partial circuit is required by an element included in another partial circuit, i.e. when a demand has been sensed, only then are the events which occurred before evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.