Use of a capping layer to attain low titanium-silicide sheet resistance and uniform silicide thickness for sub-micron silicon and polysilicon lines
US5593924A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A titanium-silicide process using a capping layer to reduce the silicide sheet resistance. A layer of titanium (20) is deposited. A react capping layer (22) may then be deposited to prevent contaminants from entering the titanium layer (20)during the subsequent react step. The layer of titanium (20) is then reacted to form titanium-silicide (32). The react capping layer (22) is then removed and an anneal capping layer (36) is deposited to prevent contaminants from entering the silicide layer (32) during the subsequent anneal step. Then, the silicide anneal is performed to accomplish to transformation to a lower resistivity phase of silicide. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.