Input protection circuit formed in a semiconductor substrate
US5594265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1991 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Nov 27, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the sem…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.