J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5594275A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1994 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Nov 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having at least one semiconductor chip loaded on a lower surface of a printed circuit board, electrode terminals of the semiconductor chip wire-bonded to terminals on the printed circuit board, and a connection portion of the semiconductor chip and wires encapsulated by means of encapsulating resin includes a semiconductor device of three-dimensional structure having the printed circuit board reversely mounted, the terminals of the printed circuit board connected to external terminals via through holes, and at least one semiconductor device stacked on an upper surface of the printed circuit board, thereby interconnecting respective semiconductor devices while interposing solder balls to be mounted to other printed circuit boards by leads being the external terminals. Thus, a ball grid array (BGA) package able to be stacked inside a small out-line J-lead (SOJ) package is used for performing interconnection to make the BGA overcome a typically two-dimensional flat mounting and attain a three-dimensional surface mounting structure while being perfectly compatible with a currently-available mounting process on the main substrate, thereby improving mounting effici…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.