Logic cell and routing architecture in a field programmable gate array
US5594363A · kind A · utility
117Cited by
7References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Apr 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.