Delay circuit for a write data precompensator system
US5594377A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Sep 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A write data precompensator system is described which comprises a delay element circuit (12) which receives a clock signal and outputs a delayed clock signal which includes a programmable selectable delay in the rising edge of the clock signal. The amount of delay is received using a delay voltage level generated by a delay level circuit (16) which receives delay magnitude control values in digital form. A reference level circuit (18) also generates a continuous level voltage level so that the delay element circuit (12) can instantly change between a delayed operation and an undelayed operation without waiting for the delay voltage level to adjust.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.