Signal processing channel with high data rate and low power consumption
US5594436A · kind A · utility
1Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1994 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Oct 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.