SRAM cell using a CMOS compatible high gain gated lateral BJT
US5594683A · kind A · utility
29Cited by
2References
15Claims
0Family size
Inventors
Key dates
| Filing date | Apr 7, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Apr 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention presents a new SRAM cell comprising only two MOSFETs: one is the access device for data transfer; and the other is operated as a high gain gated lateral BJT in the reverse base current mode so as to constitute the role of the storage flip-flop or latch. This invention also requires only one-sided peripheral circuitry for Read/Write function. Thus the chip area is greatly saved. In addition, the invention is fully compatible with the existing low-cost, high-yield standard CMOS process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.