Random access memory (RAM) based configurable arrays
US5594698A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1994 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Nov 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable device includes two separate and electrically isolated arrays of rows and columns of conductors sharing the same area of an integrated circuit substrate, one array interconnecting memory cells to form a random access memory ("RAM"). The other array forms a full or partial cross-point switching network that is controlled by information stored in memory cells, and/or connects to an operating electronic circuit that is configurable and operable in accordance with information stored in memory cells. In addition, the memory array is easily used to access desired nodes of the circuit array in order to be able to easily observe internal signals during operation. A preferred memory structure is a dynamic random access memory ("DRAM") because of a high density and low cost of existing DRAM fabrication techniques, even though periodic reading and refreshing of the states of the memory cells is required. Several circuits and techniques are used which allow continuous assertion of the memory cell states without interruption during the their refreshing cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.