DRAM with reduced electric power consumption
US5594699A · kind A · utility
18Cited by
3References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 16, 1994 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Sep 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.