Multi-first-in-first-out memory circuit
US5594702A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Jun 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators. Each pair of pointer registers includes a read pointer register that indicates a corresponding group's next storage element to be read and a write pointer register that indicates the group's next storage element to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.