Noise resistant reset circuit for a phase detector in a phase-locked loop
US5596293A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop. The reset circuit is immune from latch race conditions and spurious latch reset operations associated with latches in prior art phase-locked loop phase detectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.