Video signal data and composite synchronization extraction circuit for on-screen display
US5596372A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Feb 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process. Frequency and phase synchronization is accomplished by a combination of frequency lock loop and phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator is not subject to noise in the incoming signal a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.