Electrically alterable n-bit per cell non-volatile memory with reference cells
US5596527A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.