Single clock scan latch
US5596584A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.