Method and apparatus for testing high speed busses using gray-code data
US5596715A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Aug 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for providing data to an I/O bus at the maximum I/O bus bandwidth comprises an exerciser unit coupled to the I/O device. The exerciser unit includes DMA circuitry for providing a constant stream of transactions to the I/O bus. Each transaction provides a plurality of data quadwords to the I/O bus which are parity protected. The exerciser unit includes a memory device for storing data to be provided for each transaction, and a parity circuit for calculating and providing parity for the data stored in the memory. The exerciser unit further includes a data generation device for providing both data having predictable parity and the parity to the bus for each bus cycle while bypassing the parity generation logic to provide data at maximum bandwidth. The data generation device provides a sequence of different data bytes using a modified Gray-code algorithm, which facilitates parity generation for each byte in the sequence of bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.