Four state token passing alignment fault state circuit for microprocessor address misalignment fault generation
US5596717A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention employs a token passing structure for controlling alignment fault generation. This alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. If the token is present in a particular latch, then the corresponding state is active. If the token is absent, then the corresponding state is inactive. The presence of the token in a predetermined one of the four states causes a fault gate qualifier signal to be active permitting fault generation on address misalignment. Absence of the token from that state causes the fault gate qualifier signal to be inactive prohibiting fault generation on address misalignment. This structure efficiently implements address misalignment fault control by means of token location. Every token location is accessible at every privilege level. An additional instruction not previously supported by Intel microprocessors and Intel compatible microprocessors permits the application program access to the individual token locations and thus to all the permitted states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.