Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks
US5596740A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Jan 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the shared interleaved memory by way of asserting a priority signal, an address, and an operand size which are decoded to discern which, if any, memory banks in the interleaved shared memory are needed. In the event of a bank request conflict, the highest priority requester gets all its requested banks and the losing requester gets all nonconflicting requested banks. After the banks in the interleaved memory are allocated, a signal identifying that the losing requester did not receive all its requested banks is generated which does not impact the delay in the data path and accordingly, the losing requester resubmits its request on the next cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.