Highly-planar interlayer dielectric thin films in integrated circuits
US5598028A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.