High speed reduced area multiplexer
US5598114A · kind A · utility
23Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1995 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.