Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays
US5598408A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1994 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Jan 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.