Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles
US5598551A · kind A · utility
61Cited by
18References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1996 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Feb 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.