Error free data transfers
US5598552A · kind A · utility
2Cited by
14References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1994 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Aug 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A novel circuit is provided which allows a storage register to load data from another register utilizing a store signal which is asynchronous to the clock signal used to store data in the first register. A novel store circuit is provided which provides a control signal in response to a store signal, which conditionally loads data into the storage register. The contents of the storage register is either maintained or overwritten, depending upon the relationship of the store signal to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.