Methods of fabrication of submicron features in semiconductor devices
US5599738A · kind A · utility
7Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1995 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Dec 11, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of fabricating submicron features including depositing a gate metal layer on a substrate and forming a first etchable layer of material on the metal layer to define a first sidewall. A second etchable layer is deposited on the structure so as to define a second sidewall. The second etchable layer is etched so as to leave only the second sidewall and the first etchable layer is removed. The metal layer is etched using the second sidewall as an etch mask to form a submicron feature. The width of the feature depends upon the thickness of the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.