Low power consumption comparator circuit
US5600269A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1994 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Dec 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only while the circuit is at the latch operation. Since a current-consumption is at a zero-state during the normal operation of the comparator circuit, the comparator circuit has a low…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.