Method of graphically displaying and manipulating clock-based scheduling of HDL statements
US5600567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1994 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Nov 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16). The update alters values in the design database (18) to reflect the present scheduling information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.