Semiconductor memory device with reduced consumption power for bit line precharge
US5600601A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 28, 1994 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Dec 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed for use in writing and reading data. The memory device is provided with a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to each of the word lines and bit lines, respectively. The memory device is provided with a precharger which precharges to set the potential of each bit line to a given level before the data on the memory cells can be read out onto the bit lines. The memory device is responsive to an address signal, and a controller for controlling the precharger. The controller activates the precharger so that all the bit lines are precharged when a previously selected word line changes following the change of the address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.