FIFO fail-safe bus
US5600786A · kind A · utility
5Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1995 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Aug 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is an apparatus which utilizes relatively few conductors to provide fail-safe communication between multiple electrical subsystems and a redundant pair of data processors. This is accomplished by including two first-in, first-out memory units within each electrical subsystem, and utilizing these memory units to send the output data from the electrical subsystems on a pair of parallel data buses to a redundant pair of data processors, which then perform error tests on the data to ensure its integrity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.