Vector move instruction in a vector data processing system and method therefor
US5600811A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1995 |
| Grant date | Feb 4, 1997 |
| Priority date | — |
| Expiry date | Aug 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A "vnmvh" instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing elements in the vector data processor participate in the function regardless of a setting of a status bit (Vt bit) (FIG. 6). During execution of the vnmvh instruction, the least significant bits of vector register specified in an operand are negated and moved into a plurality of history bits (Vh bits) (FIG. 6). The functionality provided by execution of vnmvh instruction allows a user to execute a nested conditional construct efficiently and effectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.