Ion Implantation buried gate insulator field effect transistor
US5602403A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 1991 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Mar 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A buried, gate insulator field effect transistor is disclosed. It comprises a source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are excised into this covering layer to allow electrical connection to the source, substrate, drain, and gate. The substrate and gate are vertically aligned in the resulting structure. The source, drain and gate are fabricated from a doped, semiconductor of one polarity while the substrate is fabricated from doped semiconductor of the opposite polarity. The gate insulator layer is fabricated by implanting an element or elements selected from Group V, VI or VII into the semiconductor to form a semiconductor-compound insulator. Methods of fabricating this device are also disclosed. In one embodiment the device is fabricated on top of an insulating support. The gate is formed next to the base. In a second embodiment, no base is used. The gate insulator is formed between the gate and substrate. In both cases the gate insulator is formed within the semiconductor in a buried and protected mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.