Damascene conductors with embedded pillars
US5602423A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed which uses an embedded pillar 38 to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors during fabrication, particularly where such conductors are relatively large. The device comprises an insulating layer 22 formed on a substrate 20 and having a substantially planar upper surface with a plurality of channels 26, 34 formed therein. Channel 34 may be described as comprised of contiguous narrow channel segments (including right segment 40, top segment 41, and left segment 42) enclosing pillar 38, which has a top surface substantially coplanar with the upper surface of layer 22. In one embodiment, pillar 38 is formed integrally as part of layer 22. In alternative embodiments, pillar 38 may be formed from an additional insulating or conducting layer. The device further comprises conductors inlaid in the channels such that the top surface of the conductors is substantially coplanar with the upper surface of layer 22, with at least one of the conductors comprising a set of contiguous conducting segments (e.g. including 44, 46) inlaid so as to surround pillar 38.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.