Mixer circuit using a dual gate field effect transistor
US5602501A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Dec 5, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/873
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a mixer circuit, a first gate electrode of a dual gate MESFET having a pulse doped structure is connected through a filter to an LO signal input terminal, and a second gate electrode of the dual gate FET is connected through a matching circuit to an RF signal input terminal. The drain electrode of the dual gate FET is connected through a low-pass filter to an output terminal. The gate bias point of the first gate electrode 25a of the dual gate FET is set in the vicinity of the pinch-off point of the mutual conductance, and the gate bias point of the second gate electrode 25b of the dual gate FET is set in the area where the mutual conductance is unvaried with increase of the gate voltage. With this arrangement, the mixer circuit is so designed that the isolation characteristic of the RF signal and the LO signal is excellent, and a stable operational characteristic is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.